Switchable clock circuit for microprocessors to thereby save power
US5254888A · kind A · utility
95Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1992 |
| Grant date | Oct 19, 1993 |
| Priority date | — |
| Expiry date | Mar 27, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power dissipation of a CMOS circuit such as a microprocessor is reduced by dynamically slowing down the microprocessor clock during selected system operations such as hold, wait, or AT peripheral bus access cycles. The microprocessor clock is slowed to its minimum allowable frequency with precise synchronous control to maintain the accuracy of high frequency clock edges and to prevent glitches or substandard pulse widths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.