Phase-lock-loop circuit and method for compensating, data bias in the same
US5254958A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1992 |
| Grant date | Oct 19, 1993 |
| Priority date | — |
| Expiry date | Sep 30, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Biomedical information is directly digitally telemetered from the patient through a frequency modulated transmitter to a remote receiver and computer station. A phase-lock-loop circuit in the digital transmitter compensates for DC data bias by averaging and generating a scaled measure of the DC content of the digital data fed into the phase-lock-loop circuit. The average signal is then provided as a control signal to a first voltage controlled crystal oscillator, the output of which is then used as a reference frequency for the phase-lock-loop circuit. Frequency modulation of the digital data is provided by coupling the digital data directly into the voltage control input of the voltage controlled oscillator which generates the output frequency. Further control of the phase-lock-loop circuit in the transmitter is achieved by prepositioning the operating frequency of the voltage controlled oscillator by means of a microcontroller. The input to the microcontroller is a digital word corresponding to the desired frequency. The microcontroller then uses an algorithm to set the operating frequency of the voltage controlled oscillator at a preselected point within the bandwidth of the pha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.