Electrostatic discharge detection and clamp control circuit
US5255146A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1991 |
| Grant date | Oct 19, 1993 |
| Priority date | — |
| Expiry date | Aug 29, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A switching element is connected to an integrated circuit for shunting an ESD pulse away from the integrated circuit features. A plurality of detection circuits responsive to typical ESD waveform characteristics provide logical control of the switching means. In the preferred embodiment, a NAND gate drives the switching element. The first input to the NAND gate is a first RC network having a first time constant that exceeds the characteristic rise time of the typical ESD pulse, but not the characteristic duration of the typical ESD pulse. The second input to the NAND gate is a feedback loop from the NAND gate output. The feedback loop includes a second RC network having a second time constant that exceeds the duration of a noise pulse, a third RC network having a third time constant that approximates the characteristic duration of the typical ESD pulse, and an inverter between the second and third RC networks. Application of the ESD pulse causes the first input to drive the NAND gate, thus turning on the switching element, and if the ESD pulse is still present when the second time constant is exceeded, the switching means is latched on via the second input until the third time cons…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.