Reduced hardware look up table multiplier
US5255216A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1991 |
| Grant date | Oct 19, 1993 |
| Priority date | — |
| Expiry date | Aug 16, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/0356
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for multiplying an N bit number X(t) by an M bit number O, and a method for making such an apparatus for multiplying numbers are described. The N bit number is partitioned into K non-overlapping bit groups having priorities ranging from 0, which corresponds to the least significant bits in the value X(t), to K-1, which corresponds to the most significant bits in the value X(t). Each bit group functions as an address which accesses a first value in a respective Look Up Table (LUT). The values from the respective LUTs represent a sum of a constant, which is different for different LUTs, and the product of C and the binary value of the bit group to which the LUT corresponds. The values of the LUTs are added together, effectively bit shifted in accordance with their relative priorities, to form a partial product. The process is repeated with the remaining bit groups of X(t) in their order of priority, highest to lowest. An adder partial products until a single result is obtained. The single result is the (N+M) bit product of C and X(t). the correct result for this product is obtained from the adder tree because the individual constants added to the LUTs, which co…
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