Method and apparatus for testing the continuity of static random access memory cells
US5255230A · kind A · utility
45Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1991 |
| Grant date | Oct 19, 1993 |
| Priority date | — |
| Expiry date | Dec 31, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method of testing a memory array of SRAM cells each of which includes memory transistors, bit and bit# lines, precharge circuitry, and an output test terminal involving the steps of connecting selected bit and bit# lines of selected SRAM cells to the output test terminal, disconnecting the memory transistors of the selected SRAM cells from the bit and bit# lines, disconnecting the bit and bit# lines from the precharge circuitry, enabling the column select circuitry to select the columns of the selected SRAM cells, applying a preselected level voltage to the output test terminal, and measuring any current which flows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.