Apparatus for intelligent reduction of worst case power in memory systems
US5255241A · kind A · utility
4Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 1991 |
| Grant date | Oct 19, 1993 |
| Priority date | — |
| Expiry date | May 20, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system is implemented by an array of large scale integrated dynamic random access memory elements. The memory elements are of a type that permit data way word storage on a page basis, each page being defined on a row boundary. Discovering that excess power consumption by the memory can result from successive memory operations made back-to-back to different page locations, the present invention provides counter means to count each immediately successive different page memory operations so that, when that count matches a maximum count, memory operations are stalled for a period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.