Apparatus for efficiently interconnecing channels of a multiprocessor system multiplexed via channel adapters
US5255372A · kind A · utility
10Cited by
18References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1990 |
| Grant date | Oct 19, 1993 |
| Priority date | — |
| Expiry date | Aug 31, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for efficiently interconnecting OEMI channels of a multiprocessor facility. A plurality of channel adapters are connected to individual channels from a plurality of processors. A supervisory interrupt driven microprocessor receives a link request from a channel adapter when the channel adapter has determined that two logical adapters are in an appropriate architected state. The microprocessor will assign a data bus to channel adapters involved in a link request if certain criteria is met by said link requests, signifying an efficient transfer between said channel adapters is likely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.