Gate-to-drain overlapped MOS transistor fabrication process
US5256586A · kind A · utility
19Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1991 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | Jul 5, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a gate-to-drain overlapped MOS transistor in which gate-to-drain capacitance is lower and a structure thereby. A pad oxide layer is formed over a substrate having a first conductive layer with a first pattern formed on a first gate oxide layer, and etchback process is performed until surface part and a predetermined upper parts of the both side walls of the first conductive layer is exposed. As a result, a second conductive layers with a second pattern is formed and a second gate oxide layer thicker than the first gate oxide layer is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.