Neural network with multiplexed snyaptic processing
US5256911A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1992 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | Jun 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an apparatus for multiplexed operation of multi-cell neural network, the reference vector component values are stored as differential values in pairs of floating gate transistors. A long-tail pair differential transconductance multiplier is synthesized by selectively using the floating gate transistor pairs as the current source. Appropriate transistor pairs are multiplexed into the network for forming a differential output current representative of the product of the input vector component applied to the differential input and the stored reference vector component stored in the multiplexed transistor pair that is switched into the multiplier network to function as the differential current source. Pipelining and output multiplexing is also described in other preferred embodiments for increasing the effective output bandwidth of the network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.