Lock detection for a phase lock loop
US5256989A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1991 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | May 3, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signal are applied to a lock detection circuit for generating a first digital output signal having a first logic state from a mutually exclusive combination of the first and second digital signals. The first logic state of the first digital output signal is compared with a time slot window formed by a control signal for generating a true lock detection signal when the first logic state of the first digital output signal occurs within the time slot window and a false lock detection signal when the first logic state of the first digital output signal occurs outside the time slot window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.