Methods and apparatus for concatenating a plurality of lower level SONET signals into higher level sonet signals
US5257261A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1992 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | May 1, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/123
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for concatenating a plurality of lower level SONET signals into higher level SONET signals are provided. In generating a higher level SONET signal (e.g., STS-12C) using a plurality of lower level SONET signal processing apparatus (e.g., STS-3 type terminators), the J1 bytes of each lower level signal are tracked through the FIFOs of the apparatus to provide J1 byte control signals, and a logic circuit is provided having phase 3 of the outgoing STS-3 clock, and the J1 byte control signals from all the STS channels of the higher level signal as inputs. The J1 byte control signals from all the channels are combined as a J1ANDcomposite by utilizing a single bus which is coupled to each of the apparatus. The logic circuit inhibits a read of a J1 byte from any particular FIFO unless the J1ANDcomposite signal is high at phase 3 of the clock. In addition to the J1 byte circuitry, the lower level SONET signal processing apparatus are coupled to adjacent apparatus so that the B3 parity byte value from one apparatus is passed to the next apparatus for inclusion in its calculation of the B3 parity byte. Eventually, the master apparatus calculates a B3 parity byte for the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.