Narrow radius tips for high voltage semiconductor devices with interdigitated source and drain electrodes
US5258636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1991 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Dec 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
Abstract
A field effect transistor (FET), according to the present invention, comprises a source and drain pair of electrodes having non-uniform charge distributions between them, such as results from small radius tips, and has a gate and channel structure that exists only between points of the source and drain pair that have the less intense charge distributions, e.g., areas not involving any small radius tips. The gate and channel structure is such that, given the non-uniform charge distributions between the source and drain pair of electrodes, the electric field is reduced around the tip by eliminating the n-well junction near the source-drain fingertips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.