Semiconductor device having MOS transistor and a sidewall with a double insulator layer structure
US5258645A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 1992 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Sep 4, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
A semiconductor device including a semiconductor substrate with a P-type well formed in the semiconductor substrate and a gate insulator layer formed on the semiconductor substrate. N-type diffusion regions are formed in the P-type well on both sides of the gate insulator layer. A gate electrode is formed on the gate insulator layer, where the gate electrode has top and side surfaces. The gate electrode and the N-type diffusion regions respectively form gate, source and drain of a N-channel MOS transistor. An insulating layer covers a portion of the N-type diffusion regions, the side surfaces of the gate electrode and at least a portion of the top surface of the gate electrode. The side wall layer which is made of an insulating material is formed on the insulating layer to provide a smooth coverage around the side of the gate electrode and aligns with an edge of said insulating layer which stops covering the N-type diffusion regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.