Frequency synthesizer
US5258724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1983 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Dec 30, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/187
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The fractional division frequency synthesizer comprises a digital ramp generator producing a digital correction ramp controlled by a frequency control programmer; a divide by N divider coupled to an output of a voltage controlled oscillator with the divider being controlled by the program, where N is a selected one of an integer and a fraction one or greater; a digital phase detector coupled to a reference clock and the output of the divider to provide a digital phase error signal; a digital adder coupled to an output of the ramp generator and the phase detector to produce a ramp corrected digital phase error signal; and circuit arrangement coupled to an output of the adder and a control input of the controlled oscillator to convert the ramp corrected digital phase error signal to a ramp corrected analog phase error signal to control the controlled oscillator and thereby provide a controlled frequency signal at the output thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.