Timing control for PRML class IV sampling data detection channel
US5258933A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1992 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Aug 27, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-mode timing loop for a PR4,ML sampled data channel includes an analog to digital converter and a digital finite impulse response filter for providing conditioned digital samples. The timing loop includes a reference clock source for putting out a reference clock frequency related to a nominal sample data rate, a frequency controllable oscillator connected to generate a sample clock, an analog timing loop and a digital timing loop. The analog timing loop provides phase lock during non-data read mode, and during data read mode the digital timing loop provides a vernier offset for fine adjustment of phase lock to a static setting then provided by the analog timing loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.