Memory cell sense technique
US5258948A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1992 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Feb 3, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell sense technique for sensing a logic state of a memory cell. An output level translator (33) which can be preset to a predetermined logic state is utilized. A current source circuit (24) and a current sink circuit (26) change memory cell sensing into two distinct modes. In the first mode, the memory cell logic state is identical to the preset output logic state. The memory cell generates a differential voltage which is countered by a differential voltage created by the current source and current sink circuit. Inputs to a sensing circuit common mode and non-complemented output (44) remains in the preset logic state. In the second mode, the current source circuit and current sink circuit aid the memory cell in generating a differential voltage. The sensing circuit senses the differential voltage and changes the non-complemented output (44) from the preset logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.