Apparatus for and method of synchronizing a clock signal
US5259005A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1992 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Mar 26, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The method of synchronizing a sampling clock signal to a received data signal, the clock recovery circuit generates several clock signals at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry generates error signals representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit then adjusts or maintains the phase of the symbol clock to provide the optimal sampling phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.