Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
US5259006A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1991 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Aug 20, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch specified in the circuit configuration data. The synchronizer flip-flop is provided immediately upstream in the data path from its corresponding original user flip-flop device. A predetermined amount of delay is added to the user's original clock and data signals. A synchronizing clock signal generator provides a delayed synchronizer clock for each master clock in the circuit which is provided to each user flip flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.