High speed electrical signal interconnect structure
US5260892A · kind A · utility
46Cited by
22References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 21, 1991 |
| Grant date | Nov 9, 1993 |
| Priority date | — |
| Expiry date | Nov 21, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved high speed, high density Dynamic Random Access Memory (DRAM) electrical signal interconnect structure which has particular application to computer systems which employ Single In-line Memory Modules (SIMMs). The structure contains an on-board buffer for driving time critical signals from a single source and further includes innovative signal trace routing having approximately equivalent minimum distance signal line lengths and vias to memory modules on the front and back surfaces of the circuit board resulting in a high speed, high density SIMM with clean rising/falling signal edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.