Semiconductor memory device
US5260903A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1992 |
| Grant date | Nov 9, 1993 |
| Priority date | — |
| Expiry date | Feb 12, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device provided that first data is read out from a first memory cell within a first readout period; and second data is read out from the second memory cell within a second readout period; wherein an amplifier circuit receiving the first and second data, outputting first data signals having first electric potential level corresponding to the first and second data and outputting second data signal having second electric potential level; control circuit, in response to an external control signal, generating a first control signal in each of the first and second readout periods, the first control signal indicating first logic level during an enabling period of time within each of the first and second readout periods, otherwise the first control signal indicating second logic level; a first latch circuit latching the first data signals in the respective first and second readout periods and outputting a first latched data signal at the time of the first control signal indicating the first logic level; a second latch circuit latching the second data signals in the respective first and second readout periods and outputting a second latched data signal at the time of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.