Programable interrupt controller
US5261107A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1992 |
| Grant date | Nov 9, 1993 |
| Priority date | — |
| Expiry date | Jan 23, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable interrupt controller having a plurality of interrupt request inquest inputs and an interrupt request output for connection to a central processing unit (CPU) includes means for interrupting the CPU over the interrupt request output responsive to an interrupt request from any one of the interrupt request inputs and a priority resolver for assigning a priority position to each of the interrupt request inputs to create an interrupt priority hierarchy. The interrupt controller is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.