Nitride polish stop for forming SOI wafers
US5262346A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1992 |
| Grant date | Nov 16, 1993 |
| Priority date | — |
| Expiry date | Dec 16, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a SOI integrated circuit includes defining thin silicon mesas by wet etching a device layer having the <100> orientation down to the underlying insulator so that the (111) crystal planes control the lateral etching, forming a nitride bottom polish stop in the bottom of the apertures by a low temperature CVD process, with nitride sidewalls on the (111) planes of the silicon mesas being susceptible to easy removal, so that no hard material is present during a chemical-mechanical polishing step to thin the device layer down to less than 1000 .ANG., and filling the apertures with a temporary layer of polysilicon to provide mechanical support to the edges of the device layer during the polishing operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.