Process for manufacturing a multilayer integrated circuit interconnection
US5262351A · kind A · utility
86Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1991 |
| Grant date | Nov 16, 1993 |
| Priority date | — |
| Expiry date | Jul 23, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/98
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention is a method of producing a multilayer polymer-metal system to interconnect integrated circuits which allows two-dimensional electrical and/or optical connections between components, in which a first layer of polymer is deposited on a rigid substrate such that the layer can be separated from the substrate, in which a multilayer interconnection system is then produced on this first layer using industrial methods and in which the rigid substrate is removed after installation and connection of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.