Variable delay clock circuit
US5262690A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1992 |
| Grant date | Nov 16, 1993 |
| Priority date | — |
| Expiry date | Apr 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/13
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed clock delay circuit in which an external differential digital clock signal is connected to a pair of differentially connected, current switching transistors. Emitter follower drivers couple the switching transistors to differential delayed clock output terminals. A pair of diodes cross-coupled between the differential output terminals and the switching transistors provide a relatively large Miller Effect capacitance, the charging and discharging of which provides a delay in the switching of the transistor pair, as measured differentially. Changing the charging and discharging current through the emitter follower driver, changes the bias across the diodes and thus changes their effective capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.