Error detection in the basic processing unit of a VLSI central processor
US5263034A · kind A · utility
13Cited by
8References
5Claims
0Family size
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Key dates
| Filing date | Oct 9, 1990 |
| Grant date | Nov 16, 1993 |
| Priority date | — |
| Expiry date | Oct 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.