Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems
US5263139A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1992 |
| Grant date | Nov 16, 1993 |
| Priority date | — |
| Expiry date | May 19, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple bus architecture for flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The multiple bus architecture enables flexible communication between processors and devices coupled to a multiprocessor bus, a system interconnect bus, an external bus, an input/output bus, and a memory subsystem. Processor modules coupled to multiprocessor bus slots access the memory subsystem over the multiprocessor bus. System interconnect modules coupled to system interconnect bus slots access the memory subsystem via the system interconnect bus, and the multiprocessor bus. Processor modules coupled to multiprocessor bus slots access devices on the external bus via the system interconnect bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.