Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles
US5263149A · kind A · utility
37Cited by
7References
6Claims
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Key dates
| Filing date | Feb 19, 1991 |
| Grant date | Nov 16, 1993 |
| Priority date | — |
| Expiry date | Feb 19, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware simulator comprises a plurality of interconnected programmable logic devices (20) which are connected via a data bus (22) and a control bus (24). Address signals on control bus (24) are read by an interconnect logic block (18) associated with each device to selectively link the output latches and input latches of the devices (20) to the data bus (22). Accordingly, a series of signal transfers is carried out between the devices simulating the hardware. The interconnect logic blocks may be programmed to provide whatever connections between devices are required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.