Bus arbitration and resource management for concurrent vector signal processor architecture
US5263169A · kind A · utility
60Cited by
20References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 20, 1991 |
| Grant date | Nov 16, 1993 |
| Priority date | — |
| Expiry date | Oct 20, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A concurrent vector signal processor includes a resource manager for utilization of captive signal processing resources. The first instructions in a temporary instruction queue are predecoded and the signal processing resources are selected to execute those first instructions. Arbitration system is provided for external buses connected to a concurrent vector signal processor. A processor arbiter supervises on a priority basis both captive processor resources and independent processor resources. A bus arbiter supervises on a priority basis external and internal buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.