High speed arithmetic and logic generator with reduced complexity using negative resistance
US5265044A · kind A · utility
Inventor
Key dates
| Filing date | Oct 10, 1990 |
| Grant date | Nov 23, 1993 |
| Priority date | — |
| Expiry date | Oct 10, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4828
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique for generating a carry, AND, OR, NAND, NOR, INVERTING logic and sum and carry: operation in a one or at most two device delay by employing negative differential resistance devices. Circuits implemented with this technique are not only extremely fast, but use a small number of active devices as well. This technique could be implemented in building circuits using any transistor Bipolar Transistors, Field Effect Transistors (FETs), High Electron Mobility Transistors (HEMTs), Hetero-junction Bipolar Transistors (HBTs), etc. The negative differential resistance characteristics of the resonant tunneling transistor can be exploited to increase the noise margin. Resonant tunneling devices have the added advantage of working at very high speeds, and could yield propagation delays less than 5ps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.