Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a plurality of destination processors and combining responses
US5265207A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1993 |
| Grant date | Nov 23, 1993 |
| Priority date | — |
| Expiry date | Apr 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel computer comprising a plurality of processors and an interconnection network for transferring messages among the processors. At least one of the processors, as a source processor, generates messages, each including an address defining a path through the interconnection network from the source processor to one or more of the processors which are to receive the message as destination processors. The interconnection network establishes, in response to a message from the source processor, a path in accordance with the address from the source processor in a downstream direction to the destination processors thereby to facilitate transfer of the message to the destination processors. Each destination processor generates response indicia in response to a message. The interconnection network receives the response indicia from the destination processor(s) and generates, in response, consolidated response indicia which it transfers in an upstream direction to the source processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.