High performance asynchronous bus interface
US5265216A · kind A · utility
33Cited by
11References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1991 |
| Grant date | Nov 23, 1993 |
| Priority date | — |
| Expiry date | Jun 28, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface coupling an asynchronous bus and a slave device, such as a memory. The bus interface comprises an asynchronous bus controller and a synchronous bus controller. The asynchronous bus controller is implemented as two state machines. One state machine controls the connection and disconnection phases of the bus protocol, while the other controls the data transfer phase. The synchronous bus controller controls data transfer between the bus and the slave device. The state machines are closely interlinked to each other and the synchronous bus controller allowing for increased bus efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.