Method and apparatus for providing total and partial store ordering for a memory in multi-processor system
US5265233A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 17, 1991 |
| Grant date | Nov 23, 1993 |
| Priority date | — |
| Expiry date | May 17, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved memory model and implementation is disclosed. The memory model includes a Total Store Ordering (TSO) and Partial Store Ordering (PSO) memory model to provide a partial order for the memory operations which are issued by multiple processors. The TSO memory model includes a FIFO Store Buffer for Store, and Atomic Load-Store operations. The Load operations are not placed in the FIFO Store Buffer. The Load operation checks for a value stored in the same location in the FIFO Store Buffer; if no such value is found, then requested value is returned from memory. The PSO model also includes a Store Buffer for Store, and Atomic Load-Store operations. However, unlike the TSO model, the Store Buffer in the PSO model is not FIFO. The processors in the PSO model may issue the Store and Atomic Load-Store in a certain order; however, such operations may be executed by memory out of the order issued by the processors. The execution order is assured only by address matching and the STBAR operation. Two Store operations separated by a STBAR operations guarantees memory will execute the operations in an order issued by the processors. Load operations in the PSO model are not placed in the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.