Self-aligned gated electron field emitter
US5266530A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1991 |
| Grant date | Nov 30, 1993 |
| Priority date | — |
| Expiry date | Nov 8, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a self-aligned gated electron field emitter. An oxidation process forms an optimized, atomically sharp needle (18) in a silicon substrate (12). The needle and surrounding planar area are conformally coated with silicon dioxide (22). A dielectric layer (24) is deposited and planarized over the needle. The dielectric layer is then partially etched away so as to expose the coated needle. The silicon dioxide exposed on the needle is isotropically etched so as to undercut the dielectric layer. A gate metal is directionally deposited so as to form a gate layer (26) on the planar portions of the dielectric layer that is electrically isolated from the gate metal (28) deposited on the needle. The metal on the needle is anodically etched by applying the potential only to the silicon and not to the gate layer. Electro-plating may recoat the needle with another metal (30). The silicon substrate may be replaced by a glass substrate (42) on which is deposited a polysilicon or amorphous silicon layer (40). The invention allows the fabrication of an array of emitters with closely spaced gates over large areas and on inexpensive substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.