Tri state buffer circuit for dual power system
US5266849A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1992 |
| Grant date | Nov 30, 1993 |
| Priority date | — |
| Expiry date | Feb 19, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS tri-state buffer circuit transfers digital signals between a first digital circuit system operating at 3.3 Volts and a second system operating at 5 Volts. The buffer circuit receives an active high enable signal and a data signal as inputs to a tri-state select network. When the enable signal is high, data is propagated through a driver stage and onto a data bus in the second system. Driver clamp circuitry and an n-well voltage controller operate conjunction with the driver stage to prevent the 5 volt supply of the second system from interfering with the circuitry of the of the 3.3 Volt system. A clamped line driver transmits signals from the 5 Volt system to the 3.3 Volt system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.