Clock delay trim adjustment with stopping feature for eliminating differential delay between clock signal and analog signal
US5266850A · kind A · utility
5Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1992 |
| Grant date | Nov 30, 1993 |
| Priority date | — |
| Expiry date | Jun 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Method and circuitry for phase synchronizing an analog input signal with a clock signal by sensing clock delay error, adjusting in increments clock delay trim of a delay element that initially has an arbitrary delay setting, and stopping adjustment after differential delay between the signals has been eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.