Bias circuitry for content addressable memory cells of a floating gate nonvolatile memory
US5267213A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1992 |
| Grant date | Nov 30, 1993 |
| Priority date | — |
| Expiry date | Mar 31, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power bias voltage generation circuitry for content addressable memory cells for a nonvolatile memory is described. The bias circuitry is comprised of a source follower pair and two cascaded high impedance voltage dividers. The source follower pair acts as a positive feedback loop coupling between the two high impedance voltage dividers for relatively quickly charging and settling the output node to a predetermined voltage level. The first high impedance voltage divider can relatively quickly provide an input signal to trigger the small-input-load second high impedance voltage divider. The second high impedance voltage divider comprised of two high impedance diode stacks allows most current drawing from the power supply to drive a relatively large output loading during switching. Both first and second high impedance voltage dividers help keep the DC current of the circuit to a relatively low level which helps to reduce the total power consumption of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.