BICMOS local address transition detection circuit
US5267216A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1992 |
| Grant date | Nov 30, 1993 |
| Priority date | — |
| Expiry date | Jul 27, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of local address transition detector (LATD) circuits, one per address bit signal (Ai), of the type used in SRAMs to generate an on-chip clock pulse (LATDSi) that insures a correct timing of internal circuits such as sense amplifiers and address decoders that are essential for a correct READ/WRITE operation of the SRAM. According to one aspect of the invention, each LATD circuit includes: a first bipolar transistor (T1) serially connected with a first FET device (N1) forming a first branch; a second bipolar transistor (T2) serially connected with a second FET device (N2) forming a second branch. The first and second branches are connected in parallel between a first supply voltage (Vcc) and a common output node (N) connected to a circuit output terminal (30-i) where the output signal (LATDSi) generated by the LATD circuit (22-i) is available. The first and second bipolar transistors (T1, T2) are respectively driven by the address signal (Ai') and its complement (Ai') at the ECL voltage levels and the second and first FET devices are respectively driven by the address signal (Ai*' ) and its complement (Ai*') at the CMOS voltage levels. As a result of this design of the LA…
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