Apparatus and method for simultaneously presenting error interrupt and error data to a support processor
US5267246A · kind A · utility
22Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1988 |
| Grant date | Nov 30, 1993 |
| Priority date | — |
| Expiry date | Jun 30, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2736
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for collecting and analyzing machine check interrupts generated by a central processor complex. Each logic card is scanned to detect the presence of error data generated by logic circuits on the card. A primary maintenance interface card collects the interrupt information identifying the interrupt as to type of interrupt and location of the card generating the interrupt. A system support adapter reports the collected interrupt information over a LAN to a support processor which may thereafter initiate diagnostic operations with the central processor complex.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.