Method of forming isolated wells in the fabrication of BiCMOS devices
US5268312A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1992 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Oct 22, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.