Method of increasing the accuracy of an analog circuit employing floating gate memory devices
US5268320A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 1992 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Apr 9, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/91
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for increasing the accuracy of an analog neural network which computers a sum-of-products between an input vector and a stored weight pattern is described. In one embodiment of the present invention, the method comprises initially training the network by programming the synapses with a certain weight pattern. The training may be carried out using any standard learning algorithm. Preferably, a back-propagation learning algorithm is employed. Next, the network is baked at an elevated temperature to effectuate a change in the weight pattern previously programmed during initial training. This change results from a charge redistribution which occurs within each of the synapses of the network. After baking, the network is then retrained to compensate for the change resulting from the charge redistribution. The baking and retraining steps may be successively repeated to increase the accuracy of the neural network to any desired level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.