CMOS device and process
US5268590A · kind A · utility
47Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1992 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Oct 8, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/915
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.