Device and method for automatically adjusting a phase-locked loop
US5268655A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 27, 1992 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | May 27, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-adjusting phase-locked loop (PLL) parameter adjusting device (APAD) (100) and method that automatically adjusts a phase-locked loop to provide tracking ability when and where needed, as opposed to utilizing a PLL adjusting device with preset parameters, thus maintaining minimal possible noise bandwidth. The method utilizes (1) successively integrating the PLL error output signal over a number of samples to provide a plurality of sums, (2) checking a predetermined number of sums and recording and counting the sign of each sum, (3) comparing the counted record to a predetermined threshold value, and (4) automatically adjusting PLL parameter(s) and the sample number in accordance with a predetermined strategy, such that adjusted PLL parameters are provided to the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.