Timing control for a memory
US5268869A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1990 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Oct 11, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common wordline (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell. A plurality of said dummy cells (22) has a bit value stored therein and is connected to a dummy wordline and the remainder of said dummy cells are rendered inactive, whereby on addressing of the dummy wordline simultaneously with the wordline of an accessed cell, a predetermined number of dummy cells discharges via the dummy bit line so that the voltage developed on the dummy bit line bears a predetermined relationship to the voltage differential developed between the bit lines of the accessed cell. The timing circuit (16) is connected to receive the voltage differential …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.