Memory architecture for storing twisted pixels
US5269003A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1992 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Oct 21, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement for addressing a frame buffer memory including apparatus for selecting from the address bits designating a position in the frame buffer of a pixel to be displayed on an output display the bits indicating the word address of the pixel in a particular row of the frame buffer, apparatus for multiplying the word address by a fraction to provide a new word address, apparatus for recombining the new word address with the row address to provide a new address in the frame buffer for the information regarding the pixel to be displayed, and apparatus for controlling the storage of a data word describing the pixel beginning at a selected byte of the data word whereby the storage in the frame buffer of an unused portion of a data word describing the pixel may be eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.