Byzantine resilient fault tolerant shared memory data processing system
US5269016A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1990 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Sep 24, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant data processing system which provides single fault Byzantine resilience which system uses a number of fault containment regions each of which includes at least one processing element. The fault containment regions of the system are arranged to utilize a shared memory, each of such regions including a portion of the shared memory. The shared memory portion of each fault containment region provides communication with the shared memory portions of each of the other fault containment regions. A shared memory portion includes an encoder for encoding a data byte from the processor in the region into a number of data byte symbols from which the data byte can be reconstructed. The data byte symbols can be stored in the shared memory portion of the region and can be transmitted to one or more of the shared memory portions of the other fault containment regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.