Fabrication process of a semiconductor device having a reduced parasitic capacitance
US5270249A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 6, 1992 |
| Grant date | Dec 14, 1993 |
| Priority date | — |
| Expiry date | Mar 6, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/009
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication process of a semiconductor device comprises the steps of providing a temporary layer on a semiconductor substrate, patterning the temporary layer to form a temporary protection pattern on the semiconductor substrate such that the temporary protection pattern has a pair of opposing side walls extending generally vertically, relatively to the semiconductor substrate, forming a first conductor layer, having incorporated therein an impurity element of a first conductivity type, so as to bury the temporary protection pattern therebeneath, patterning the first conductor layer to form a pair of first type conductor regions contiguous the respective, opposing side walls of the temporary protection pattern, removing the temporary protection pattern selectively with respect to the first type conductor regions thereby to leave the pair of first type conductor regions on the substrate, forming a second conductor layer such that the second conductor layer buries the first type conductor regions therebeneath, patterning the second conductor layer such that only a region thereof remains between the pair of first type conductor regions, as a second type conductor region, and forming …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.