Multiply and divide circuit
US5270962A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 1993 |
| Grant date | Dec 14, 1993 |
| Priority date | — |
| Expiry date | Mar 11, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply and divide circuit having full bit level pipeline capability uses an array of bit level carry-save adders with each carry-save bit adder having a corresponding absolute value bit circuit. In one or two's complement notation, the carry-save adders subtract the binary values supplied thereto and generate an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary numbers supplied thereto. In one mode of operation, the circuit can be used to perform division. In another mode of operation, the circuit can be used to perform multiply and accumulate operation, again with bit level pipeline capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.