Unidirectional bus system using reset signal
US5271008A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 1992 |
| Grant date | Dec 14, 1993 |
| Priority date | — |
| Expiry date | Jan 6, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/417
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communications system has a plurality of stations (S.sub.1, S.sub.2 . . . S.sub.N) interconnected by a pair of lines (10,11) so that one line (10) permits the stations (S.sub.1, S.sub.2 . . . S.sub.N) to transmit in one direction and the other line (11) permits transmission in the other direction. Frames each having a control field and a data field pass down the lines (10,11) and each station (S.sub.1, S.sub.2 . . . S.sub.N) can write a packet of data to any frame in which the data field is empty. This is signalled by a busy bit in the control field. The stations (S.sub.1, S.sub.2 . . . S.sub.N) are arranged to write data packets in cycles. The commencement of such a cycle for writing to signals on one line (10,11) is determined by a signal on the other line (11,10). That signal may be constituted by a suitable reset bit in the control field of a frame. Preferably, once the cycle of a station (S.sub.1, S.sub.2. . . S.sub.N) commences, it is temporarily inhibited from being recommenced by a reset signal on the other line (11, 10). The system may be implemented in folded and dual bus embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.