Multi-dimensional error diffusion technique
US5271070A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1992 |
| Grant date | Dec 14, 1993 |
| Priority date | — |
| Expiry date | Nov 6, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/4052
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit for increasing the speed of conversion of image pixels from one number of bits to another by processing a plurality of pixels in parallel. The conversion of each pixel typically results in a new value and an error term which is divided up among adjacent pixels. By using a plurality of separate conversion circuits, one for each line, and by processing the xth pixel on one line in parallel with the x-2 pixel on the next line, the plurality of pixels can be processed in parallel. All circuits are identical except that the first circuit must get the error term of the line above it from memory, and the last of the parallel circuits must store in memory the error term for the next plurality of lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.