Method for planarizing a layer of material
US5272117A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1992 |
| Grant date | Dec 21, 1993 |
| Priority date | — |
| Expiry date | Dec 7, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a planarized layer of material starts by providing a substrate (12). An integrated circuit layer (14) is formed overlying the substrate (12). A first layer of material (16) is formed overlying the integrated circuit layer (14). An etch stop layer (18) is formed overlying the layer of material (16) and etched to form sidewall formations or spacers. A second layer of material (20) is formed overlying the layer of material (16) and the etch stop layer (18). Planarization, polishing, or etch-back processing is performed using the etch stop layer (18) to endpoint. The resulting planarized layer has a thickness which is determined accurately by the etch stop layer (18).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.